GS2970A Datasheet, PDF (113/150 Pages) Gennum Corporation – Integrated audio clock generator

4.21.2 SD Audio Core Registers
NOTE: The GS2970A only accepts write/read commands to/from the SD Audio Register
Map when the audio core is locked to the incoming SD video format.
Table 4-28:SD Audio Core Configuration and Status Registers
Address Register Name Bit Name
400h
CFG_AUD
RSVD
ALL_DEL
MUTE_ALL
ACS_USE_SECOND
CLEAR_AUDIO
OS_SEL
LSB_FIRSTD
LSB_FIRSTC
LSB_FIRSTB
LSB_FIRSTA
Bit Description
15-14
13
12
11
10
9-8
7
6
5
4
Reserved.
Selects deletion of all audio data
and all audio control packets.
0: Do not delete existing audio
packets
1: Delete existing audio packets
Mute all output channels.
0: Normal
1: Muted
Extract Audio Channel Status from
second channel pair.
Clears all audio FIFO buffers and
puts them in start-up state.
Specifies the audio FIFO buffer
size.
00: 36 samples deep, 26 sample
start-up count
01: 22 samples deep, 12 sample
start-up count
10: 16 samples deep, 6 sample
start-up count
11: Reserved
NOTE: The default 36-sample deep
FIFO size is not supported if each
audio channel must have the same
sample delay.
Causes the channel 7 and 8 output
format to use LSB first.
0: MSB first
1: LSB first
Causes the channel 5 and 6 output
format to use LSB first.
0: MSB first
1: LSB first
Causes the channel 3 and 4 output
format to use LSB first.
0: MSB first
1: LSB first
Causes the channel 1 and 2 output
format to use LSB first.
0: MSB first
1: LSB first
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
GS2970A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54244 - 2
September 2012
113 of 150