MB85RC04VPNF-G Datasheet, PDF (9/36 Pages) Fujitsu Component Limited. – 4 K (512 × 8) Bit I2C

MB85RC04V
• Current Address Read
If the last write or read operation finishes successfully up to the end of stop condition, the memory address
that was accessed last remains in the memory address buffer (the length is 9 bits).
When sending this command without turning the power off, it is possible to read from the memory address
n+1 which adds 1 to the total 9-bit memory address n, which consists of the 1-bit memory upper address
from the device address word input and the lower 8-bit of the memory address buffer. If the memory address
n is the last address, it is possible to read with rolling over to the head of the memory address (000H). The
current address (address that the memory address buffer indicates) is undefined immediately after turning
the power on.
Access from master
(n+1) memory address
S 1 0 1 0 A2 A1 A8 1 A
Read
Data 8bits
NP
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L"level)
N NACK (SDA is the "H" level)
• Random Read
The one byte of data from the memory address saved in the memory address buffer can be read out
synchronously to SCL by specifying the address in the same way as for a write, and then issuing another
start condition and sending the Device Address Word (R/W “1” input).
Setting values for the first and the second memory upper address codes should be the same (an example
is shown in below).
The final NACK (SDA is the “H” level) is issued by the receiver that receives the data. In this case, this bit is
issued by the master side.
S 1 0 1 0 A2 A1 A8 0 A
Address
Low 8bits
A S 1 0 1 0 A2 A1 A8 1 A
Read
Data 8bits
NP
(Input example) when reading
memory address 16FH:
1B
01101111B
1B
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
DS501-00016-2v0-E
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