MB85RC04VPNF-G Datasheet, PDF (7/36 Pages) Fujitsu Component Limited. – 4 K (512 × 8) Bit I2C

MB85RC04V
■ DATA STRUCTURE
The master inputs the device address word (8 bits) following the start condition, and then the slave outputs
the Acknowledge “L” level on the 9th bit. After confirming the Acknowledge response, the sequential 8-bit
memory lower address is input, to the byte write, page write and random read commands.
As for the current address read command, inputting the memory lower address is not performed, and the
address buffer lower 8-bit is used as the memory lower address.
When inputting the memory lower address finishes, the slave outputs the Acknowledge “L” level on the 9th
bit again.
Afterwards, the input and the output data continue in 8-bit units, and then the Acknowledge “L” level is output
for every 8-bit data.
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC04V performs the high speed write operations, so any waiting time for an ACK* by the acknowl-
edge polling does not occur.
*: In E²PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not.
It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the
start condition and then the device address word (8 bits) during rewriting.
■ WRITE PROTECT (WP)
The entire memory array can be write protected by setting the WP pin to the “H” level. When the WP pin is
set to the “L” level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's
“H” level or “L” level.
Do not change the WP signal level during the communication period from the start condition to the stop
condition.
Note : The WP pin is pulled down internally to the VSS pin, therefore if the WP pin is open, the pin status is
recognized as the “L” level (write enabled).
DS501-00016-2v0-E
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