MB85RC04VPNF-G Datasheet, PDF (5/36 Pages) Fujitsu Component Limited. – 4 K (512 × 8) Bit I2C

MB85RC04V
■ ACKNOWLEDGE (ACK)
In the I²C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually
outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and
received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow
the acknowledge signal to be received and checked. During this Hi-Z released period, the receiver side pulls
the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
• Acknowledge timing overview diagram
SCL
1
2
3
8
9
SDA
Start
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down
if the previous 8 bits data are received correctly (ACK re-
sponse).
ACK
■ MEMORY ADDRESS STRUCTURE
The MB85RC04V has the memory address buffer to store the 9-bit information for the memory address.
As for byte write, page write and random read commands, the complete 9-bit memory address is configured
by inputting the memory upper address (1 bit) and the memory lower address (8 bits), and saved to the
memory address buffer. Then access to the memory is performed.
As for a current address read command, the complete 9-bit memory address is configured and saved to the
memory address buffer, by inputting the memory upper address (1 bit) and the memory lower address (8
bits) which has saved in the memory address buffer. Then access to the memory is performed.
DS501-00016-2v0-E
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