MB85RC16 Datasheet, PDF (8/20 Pages) Fujitsu Component Limited. – Memory FRAM 16 K (2 K x 8) Bit I2C

MB85RC16
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC16 performs the high speed write operations, so any waiting time for an ACK* by the acknowl-
edge polling does not occur.
*: In E²PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not.
It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the
start condition and then the device address word (8 bits) during rewriting.
■ WRITE PROTECT (WP)
The entire memory array can be write protected by setting the WP pin to the “H” level. When the WP pin is
set to the “L” level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's
“H” level or “L” level.
Do not change the WP signal level during the communication period from the start condition to the stop
condition.
Note : The WP pin is pulled down internally to VSS pin, therefore if the WP pin is open, the pin status is detected
as the “L” level (write enabled).
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DS501-00001-2v0-E