MB85RC16 Datasheet, PDF (7/20 Pages) Fujitsu Component Limited. – Memory FRAM 16 K (2 K x 8) Bit I2C

MB85RC16
■ DATA STRUCTURE
The master inputs the device address word (8 bits) following the start condition, and then the slave outputs
the Acknowledge “L” level on the ninth bit. After confirming the Acknowledge response, the sequential 8-bit
memory lower address is input, to the byte write, page write and random read commands.
As for the current address read command, inputting the memory lower address is not performed, and the
address buffer lower 8-bit is used as the memory lower address.
When inputting the memory lower address finishes, the slave outputs the Acknowledge “L” level on the ninth
bit again.
Afterwards, the input and the output data continue in 8-bit units, and then the Acknowledge “L” level is output
for every 8-bit data.
• Device Address Word
Start 1 2 3 4 5 6 7 8 9 1 2
SCL
..
SDA
ACK
S ^{1 0 1 0} A2 A1 A0 R/W A
..
Device code
Memory Upper
Address
Read/Write code
Access from master
Access from slave
S Start Condition
A ACK (SDA is the "L" level)
DS501-00001-2v0-E
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