MB40D001 Datasheet, PDF (8/17 Pages) Fujitsu Component Limited. – D/A Converter for Digital Tuning

MB40D001
Note: After power VCCD is turned ON (or after a reset), the state of pins and registers is as follows.
Pin
AO1 to AO4
D11/AO5 to D4/AO12
D3 to D0
“L” output
Hi-Z state (input state)
Hi-Z state (input state)
State
Register
State
Shift register
Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state).
D/A register
All reset to “0”.
Parallel output register
Not defined (retain prior state).
Expander status register (ESR) All reset to “0”.
• ESR settings have priority in determining pin states. Switching between input standby state and analog output
state is enabled even when the ESR value is “1”. When the ESR value returns to “0”, the pin returns to its
previously defined state.
In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output
state.
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