MB40D001 Datasheet, PDF (3/17 Pages) Fujitsu Component Limited. – D/A Converter for Digital Tuning

MB40D001
s PIN DESCRIPTION
Pin no.
1 to 4
5 to 12
13
14
15 to 18
19
20
21
22
23
24
Symbol
AO1 to AO4
D11/AO5 to
D4/AO12
VDD*¹
VCCD*¹
D3 to D0
CLK*²
SI*²
SO
CS*²
VCCA*¹
GND
Description
D/A converter analog output pins (VDD-GND output).
(Default state: #00 setting level output)
I/O expander parallel I/O pins (VccA/GND output 0.5 VccA/0.2 VccA input), also
used as D/A converter analog output pins (VDD - GND output).
Pin state is controlled by input data.
See “Data Configuration”. (Default state: Input mode, high-impedance state.)
D/A converter reference power supply pin.
MCU interface power supply (Power supply for I/O expander).
I/O expander parallel I/O pins (VccD/GND output 0.5 VccD/0.2VccD input).
Pin state is controlled by input data.
See “Data Configuration”. (Default state: Input mode, high-impedance state.)
Shift clock input pin.
When CS = “L”, SI data is loaded into the shift register at the rise of the shift
clock signal.
Data input pin (serial input pin).
Used for 16-bit serial data input.
Data output pin (serial output pin).
First-bit (LSB) data from the 16-bit shift register is output in synchronization
with the fall of the shift clock signal. When CS = “H”, this pin is in high
impedance state.
Chip select signal input pin.
Input to shift registers is enabled when the CS signal falling edges. Shift register
contents can be executed when the CS signal rising edges.
Analog unit power supply pin (Power supply for the OP amp.).
Common GND pin.
*1: Be sure that VCCA ≥ VCCD, and that VCCA ≥ VDD.
*2: Do not leave this pin in floating state.
3