MB15F04 Datasheet, PDF (8/23 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F04
Programmable Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CC L S F A A A A A A A N N N N N NN NN NN
N N D W C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11
1 2 S ^{TX/ TX/}
RX RX
CNT1, 2 : Control bit
[Table. 1]
N1 to N14 : Divide ratio setting bits for the TX section or RX section programmable counter
(5 to 2,047)
[Table. 4]
A1 to A7 : Divide ratio setting bits for the TX section or RX section swallow counter
(0 to 127)
[Table. 5]
SWTX/RX
: Divide ratio setting bit for the prescaler (TX section : SWTX, RX section: SWRX) [Table. 6]
FCTX/RX
: Phase control bit for the phase detector (TX section : FCTX, RX section : FCRX) [Table. 7]
LDS
: LD/fout signal select bit
[Table. 8]
NOTE: Data input with MSB first.
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
RRRRRRRRRRRRRR
14 13 12 11 10 9 8 7 6 5 4 3 2 1
5
00000000000101
6
00000000000110
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
11111111111111
Note: Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
T
T
1
2
LD/fout pin state
L
L
Outputs frTX
H
L
Outputs frRX
L
H
Outputs fpTX
H
H
Outputs fpRX
8