MB15F04 Datasheet, PDF (11/23 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

s PHASE DETECTOR OUTPUT WAVEFORM
frTX/RX
fpTX/RX
LD
(FC bit = High)
DoTX/RX
Z
tWU
H
(FC bit = Low)
DoTX/RX
Z
tWL
L
MB15F04
LD Output Logic Table
TX–PLL section
Locking state / Power saving state
Locking state / Power saving state
Unlocking state
Unlocking state
RX–PLL section
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Unlocking state
LD output
H
L
L
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoTX/RX signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz
tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
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