MB15F04 Datasheet, PDF (3/23 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F04
s PIN DESCRIPTIONS
Pin No. Pin name
1
GNDRX1
2
OSCin
3
GNDTX
4
finTX
5
VccTX
6
XfinTX
7
BSCTX
8
PSTX
9
DoTX
10
BSTX
11
GNDRX2
12
DoRX
13
PSRX
14
LD/fout
15
XfinRX
16
VccRX
17
finRX
18
LE
19
Data
20
Clock
I/O
Descriptions
– Ground for RX–PLL section.
I
The programmable reference divider input. TCXO should be connected with a
AC coupling capacitor.
– Ground for the TX-PLL section.
I
Prescaler input pin for the TX-PLL.
The connection with VCO should be AC coupling.
–
Power supply voltage input pin for the TX-PLL section.
When power is OFF, latched data of TX-PLL is cancelled.
I
Prescaler complimentary input for the TX-PLL section.
This pin should be grounded via a capacitor.
Analog switch output (BSTX) control for the TX section.
I
Always pull-down the BSCTX pin when not using BSTX. (Do not leave open.)
BSCTX = “H”; outputs the DoTX state.
BSCTX = “L” ; goes to high impedance.
Power saving mode control for the TX-PLL section. This pin must be set
I
at “L” Power-ON. (Open is prohibited.)
PSTX = “H” ; Normal mode
PSTX= “L” ; Power saving mode
O
Charge pump output for the TX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
O Analog switch output for the TX selection.
– Ground 2 for the RX section.
O
Charge pump output for the RX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Power saving mode control for the RX-PLL section. This pin must be set
I
at “L” Power-ON. (Open is prohibited.)
PSRX = “H” ; Normal mode
PSRX = “L” ; Power saving mode
Lock detect signal output (LD) / phase comparator monitoring output (fout)
O
The output signal is selected by a LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
I
Prescaler complimentary input for the RX-PLL section.
This pin should be grounded via a capacitor.
–
Power supply voltage input pin for the RX-PLL section.
When power is OFF, latched data of RX-PLL is cancelled.
I
Prescaler input pin for the RX-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
I When LE is “H”, data in the shift register is transferred to the corresponding
latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
I
A data is transferred to the corresponding latch (TX-ref counter, TX-Prog.
counter, RX-ref. counter, RX-prog. counter) according to the control bit in a
serial data.
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
3