MB90580 Datasheet, PDF (69/395 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

4.2 Reset Causes
HSTX pin
RSTX pin
Power on
Power-on
detection circuit
HSTX=LÆH
Hardware standby
release detection
circuit
RSTX=L
External reset
request detection
circuit
Without periodic clear
RST bit set
Watch-dog timer
STBYC.RST bit
reset detection circuit write detection circuit
SR
F/F
Q
SR
F/F
Q
SR
F/F
Q
SR
F/F
Q
SR
F/F
Q
WTC register
Delay
circuit
WTC register read
F²MC-16LX internal bus
Figure 4.2a Reset cause bit block diagram
Address: 0000A8_H
Read/write
Initial value
7
6
5
4
3
2
PONR STBR WRST ERST SRST WTE
(R)
(R)
(R)
(R)
(R)
(W)
(X)
(X)
(X)
(X)
(X)
(1)
1
WT1
(W)
(1)
Figure 4.2b WDTC (watch-dog timer control register)
0
WT0
(W)
(1)
Bit No.
WDTC
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control
register are set. Therefore, if an external reset request and a watch-dog reset occur at the same time, both
the ERST and WRST bits are set to 1.
A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not indicate the
correct reset causes. Therefore, design software so that the other reset cause bit values are ignored while
the PONR bit is set to 1.
Table 4.2b Reset cause bits
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
(An asterisk (*) in the table means that the previous value is maintained.)
Note: A reset cause bit is cleared only by reading the watch-dog timer control register. Thus,
once a reset occurs, the corresponding reset cause bit remains 1 even if another reset
cause occurs.
MB90580 Series
Chapter 4: Clock and Reset 49