MB90580 Datasheet, PDF (235/395 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

15.4 Operation
15.4.2 Underflow operation
An underflow is defined for this timer as the time when the counter value changes from 0000H to FFFFH.
Therefore, an underflow occurs after (reload register setting + 1) counts.
If the RELD bit in the control register is “1” when the underflow occurs, the contents of the reload register is
loaded into the counter and counting continues. When RELD is “0”, counting stops with the counter at
FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is “1” at this time, an
interrupt request is generated.
Figure 15.4.2a shows the operation when an underflow occurs.
Count clock
Counter
Data load
Underflow set
Count clock
Counter
Underflow set
0000H
Reload data
-1
-1
-1
[RELD=1]
0000H
FFFFH
[RELD=0]
Figure 15.4.2a Underflow Operation
MB90580 Series
Chapter 15: 16-Bit Reload Timer (with Event Count Function) 215