MB90580 Datasheet, PDF (105/395 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

7.4 Hardware Interrupt
updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch
processing. As a result, the interrupt processing program defined by the user is executed next.
Figure 7.4.3a illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt
request in the interrupt processing program. Figure 7.4.3b is a diagram of the hardware interrupt operation
flow.
Register file
PS I
ILM
Microcode
IR
F²MC-16L•CPU
‘
Check _
Comparator

Ž
Peripheral
Enable FF
AND
Cause FF
’
Œ
Åc

Interrupt
controller
PS : Processor status
I : Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
Figure 7.4.3a Occurrence and release of hardware interrupt
x An interrupt cause occurs in a peripheral.
y The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues
an interrupt request to the interrupt controller.
z Upon reception of the interrupt request, the interrupt controller determines the priority levels of simul-
taneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corre-
sponding interrupt to the CPU.
{ The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the proc-
essor status register.
| If the comparison shows that the requested level is higher than the current interrupt processing level,
the I flag value of the same processor status register is checked.
} If the check in step | shows that the I flag indicates interrupt enable status, the requested level is
written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is
completed, then control is transferred to the interrupt processing routine.
~When the interrupt cause of step x is cleared by software in the user interrupt processing routine, the
interrupt request is completed.
MB90580 Series
Chapter 7: Interrupt 85