MB90580 Datasheet, PDF (140/395 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

11.3 Register and Register Details
11.3 Register and Register Details
11.3.1 Clock Division Control Registers
Clock Division Control Register 0, 1, 2, 3, 4
Address : 00002C_H
00002E_H
15
14
13
000034_{H MD}
—
—
000087_H
00008F_H
Read/write
(R/W) (–)
(–)
Initial value
(0)
(–)
(–)
12
11
10
9
8
Bit number
CDCR0
— DIV3 DIV2 DIV1 DIV0 CDCR1
CDCR2
CDCR3
(–) (R/W) (R/W) (R/W) (R/W) CDCR4
(–)
(1)
(1)
(1)
(1)
[bit 15] MD (Machine clock divide mode select):
This bit is used to control the operation of the communication prescaler.
0
The communication prescaler is disabled.
[initial value]
1
The communication prescaler is enabled.
[bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0):
These bits are used to determine the machine clock division ratio.
DIV3
1
1
1
1
1
1
1
1
DIV2
1
1
1
1
0
0
0
0
DIV1
1
1
0
0
1
1
0
0
DIV0
1
0
1
0
1
0
1
0
Reserved
2
3
4
5
6
7
8
Division ratio
[initial value]
Note: When the division ratio is changed, allow two cycles for the clock to stabilize before
starting communication.
Note: In actual application, please use the values other than ‘1111’.
120 Chapter 11: Communication Prescaler
MB90580 Series