MB86437 Datasheet, PDF (4/35 Pages) Fujitsu Component Limited. – 3 V Single Power Supply Audio Interface Unit (AIU)

MB86437
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Pin No.
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Symbol
SGO
STA
BBO
BTPI
BTPO
VD3
DIN
DOUT
SYNC
CLK
TCLK
VD4
SRD
SRC
STB
XPRST
LO0
LO1
LO2
LO3
PS
VS3
I/O A/D
Description
O
A
General-purpose amplifier output pin. The signal can also go to JEAR via
SW15.
Transmission analog signal output via SW1. Connect to AMP4 when
O A performing sidetone addition for reception. The standard on resistance for
the analog switch is 500 Ω.
O A Transmission analog signal output pin
I A Inverted input pin (–) for the PCM ENCODE section input op-amp
O A Output pin for the PCM ENCODE section input op-amp
P D Power supply pin for transmission. Supply a voltage between 2.7 V and 3.6 V.
I
D
PCM signal input pin. The signal is clocked in on the falling edge of CLK.
CMOS interface.
PCM signal output pin. The signal is clocked out on the rising edge of CLK.
O D After data output, becomes fixed at the "H" level if PLL synchronization is
lost or a power-down occurs. CMOS interface.
Transmission and reception sync signal input pin for the PCM CODEC
I D section. The operating clock frequency is 8 kHz. CMOS interface.
Fixing at "H" or "L" causes part of the CODEC section to power-down.
Input pin for setting the bit rate for the transmission and reception PCM
signals. The data rate can be selected from 64 kHz to 3.152 MHz for µ-law
I D or A-law operation, or from 128 kHz to 3.152 MHz for linear operation. Fixing
at "H" or "L" causes part of the CODEC section to power-down. CMOS
interface.
Clock input pin for tone generation. The internal clock divided by one or two
I D (set by D4D3 of address 01110) can be used as the tone CLK. CMOS
interface.
P D Digital power supply pin. Supply a voltage between 2.7 V and 3.6 V.
I
D
10-bit serial data input pin. CMOS interface. This data sets the electronic
volume, path, and tone settings.
I
D
Write clock input pin for the 10-bit serial data. CMOS interface.
SRD is clocked in the rising edge.
I D Strobe signal for the serial data latch. Latches on "L". CMOS interface.
I
D
Reset signal input pin for the digital circuits. CMOS interface.
L: Initialize internal latches. H: Normal
O
D
Latch output pin for external control. Outputs D0 of address 01000. CMOS
interface.
O
D
Latch output pin for external control. Outputs D1 of address 01000. CMOS
interface.
O
D
Latch output pin for external control. Outputs D2 of address 01000. CMOS
interface.
O
D
Latch output pin for external control. Outputs D3 of address 01000. CMOS
interface.
I
D
Power-down control signal input pin. CMOS interface. Powers down all
circuits regardless of register settings.
G D Digital ground pin. Set to 0 V.
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