MB81EDS256445 Datasheet, PDF (23/52 Pages) Fujitsu Component Limited. – MEMORY Consumer FCRAM CMOS 256M Bit (4 bank x 1M word x 64 bit) Consumer Applications Specific Memory for SiP

MB81EDS256445
6. WRITE (WRIT)
WRIT initiates burst write operation to an active row address. Address inputs of A[7:0] determine starting column
address and AP(A10) determines whether Auto Precharge is used or not. DQS input must be provided in order
to latch the input data. DQS must be brought to Low to satisfy the specified time duration of the Write Preamble
Setup Time to CK (tWPRES). Input data window must be guaranteed with specified minimum setup and hold time
against edge of DQS input (tDS, tDH). The input data appearing on DQ is written into memory cell array subject
to the DM input logic level appearing coincident with the input data. If a given signal on DM is registered Low,
the corresponding data will be written into the cell array. And if a given signal on DM is registered High, the
corresponding data will be masked and write will not be executed to that byte. After data input with respect to
BL is completed, DQS must be kept low for the specified minimum value of Write Postamble Time (tWPST).
Data Input Timing
CK
CK
Command
tDQSS (Min.)
DQS
DQ
DM
tDQSS (Max.)
DQS
DQ
DM
WRIT
NOP
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tDSS
Qeven
Qodd
tDS tDH tDS tDH
Mask
Qodd
tDS tDH tDS tDH
tDS tDH tDS tDH
tDS tDH tDS tDH
tDQSS
tDQSH
tDQSL
tDSS
Qeven
Qodd
tDS tDH tDS tDH
tDSH
tDSS
Mask
Qodd
tDS tDH tDS tDH
tDS tDH tDS tDH
tDS tDH tDS tDH
DS05-11456-1E
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