MB39C007 Datasheet, PDF (20/52 Pages) Fujitsu Component Limited. – 2 ch DC/DC Converter IC Built-in Switching FET & voltage detection function, PFM/PWM Synchronous Rectification, and Down Conversion Support

MB39C007
[7] Board layout, design example
The board layout needs to be designed to ensure the stable operation of this IC.
Follow the procedure below for designing the layout.
• Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through-hole
(TH) near the pins of this capacitor if the board has planes for power and GND.
• Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external
inductor (L). Group these components as close as possible to this IC to reduce the overall loop area occupied
by this group. Also try to mount these components on the same surface and arrange wiring without through-
hole wiring. Use thick, short, and straight routes to wire the net (The layout by planes is recommended.).
• Arrange a bypass capacitor for AVDD as close as possible to both the ADVV and AGND pins. Make a
through-hole (TH) near the pins of this capacitor if the board has planes for power and GND.
• The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor
(Co). The OUT pin is extremely sensitive and should thus be kept wired away from the LX pin of this IC as far
as possible.
• If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the
wiring can be kept as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor
is close to the IC's AGND pin. Further, provide a GND exclusively for the control line so that the resistor can
be connected via a path that does not carry current. If installing a bypass capacitor for the VREFIN, put it close
to the VREFIN pin.
• If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be
kept as short as possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND
pin. Further, provide a GND exclusively for the control line so that the resistor can be connected via a path
that does not carry current.
• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when
using the QFN-24 package, FUJITSU MICROELECTRONICS recommends providing a thermal via in the
footprint of the thermal pad.
• Example of arranging IC SW system parts
Co
Co
L
GND
L
VIN
Cin
Cin
VIN
Feedback line
Feedback line
1pin
GND
VIN
AVDD bypass capacitor
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DS04-27246-2E