MB86606A Datasheet, PDF (17/64 Pages) Fujitsu Component Limited. – FAST-20 SCSI Protocol Controller

MB86606A
• Interrupt status register
This register indicates the interrupt status with an 8-bit code.
• Command step register
This register indicates the execution status of each command with an 8-bit step code.
Error causes can be analyzed by referencing the interrupt status register and this register.
• Group 6/7 command length setting register
This register sets the group 6/7 command length not defined in the SCSI standard.
Setting this register determines the group 6/7 command length.
6. Receive MSG, CMD, Status Buffer (Receive MCS Buffer)
This is a 32-byte receive-only information buffer that holds the information for the message, command, and
status received from the SCSI bus.
7. Send MSG, CMD, Status Buffer (Send MCS Buffer)
This is a 32-byte send-only information buffer that holds the information for the message, command, and status
sent on the SCSI bus.
8. User Program Memory
This is a 2048-byte program memory that stores programmable commands. It can consist of 1024-byte × 2
banks or 2048-byte × 1 bank.
9. Data Register
This is a 512-byte FIFO data register that holds data in the data phase executed on the SCSI bus.
10.Burst FIFO
64-byte FIFO type data buffer to perform burst transfer during the PCI bus interface mode. The device has total
576-byte FIFO with Data Register and Burst FIFO in the PCI bus interface mode.
11.DMA Controller
This is a 32-bit DMA Controller that performs data transfer. This DMAC is a bus master during the PCI bus
interface mode.
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