MB86606A Datasheet, PDF (12/64 Pages) Fujitsu Component Limited. – FAST-20 SCSI Protocol Controller

MB86606A
4. PCI Bus Interface Mode
Pin no.
130
Pin name
PREQ
129
GNT
132, 133, 135, 136,
138, 139, 141, 142, 1, 3
to 5, 7, 9 to 11, 26 to 29, AD31 to AD0
32 to 34, 36, 38, 39, 41,
42, 44, 46 to 48
143, 13, 24, 37
C/BE3 to C/BE0
23
PAR
14
FRAME
17
TRDY
15
IRDY
20
STOP
19
DEVSEL
144
IDSEL
126
PCLK
22
PERR
125
SERR
I/O
Function
O This pin is used to request the bus arbiter for use of the bus.
I
This is the response signal input pin to the REQ signal from
the bus arbiter.
I/O PCI 32-bit address and data multiplexed pins
I/O Bus command and Byte Enable signals multiplexed pins.
This is an even parity signal pin for the AD31 to AD0 and C/
I/O BE3 to C/BE0 signals. This PAR signal becomes valid after
one clock.
I/O
This is a frame signal pin that indicates data are transferring
on the bus.
I/O Data Ready signal of Target side.
I/O Data Ready signal of Initiator (Bus master) side.
I/O
This is a stop request signal to stop the data transfer from
target to master.
Device select pin. While the device is a target, this pin
I/O
outputs the select signal that indicates the self device is
selected. While the device is a master this pin functions as
an input pin to indicate that a device on the bus is selected.
I
This is a chip select signal that indicates the configuration
access.
I
PCI bus clock input pin. The maximum clock frequency is 33
MHz.
I/O Data parity error input and output pin.
OD Address parity error output pin.
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