MB86606A Datasheet, PDF (16/64 Pages) Fujitsu Component Limited. – FAST-20 SCSI Protocol Controller

MB86606A
s BLOCK FUNCTIONS
1. Internal Processor
This processor provides the sequence control between each phase.
2. Timer
This timer manages the time specified by SCSI and the following time:
• REQ/ACK assertion time for data at asynchronous transfer
• Selection/reselection retry time
• Selection/reselection timeout time
• REQ/ACK timeout time during transfer
Asynchronous transfer (target)
: Time required for initiator to assert ACK signal after asserting REQ
signal
Asynchronous transfer (initiator)
: Time required for target to negate REQ signal after asserting ACK
signal
Synchronous transfer (target only) : Time required for target to receive ACK signal for setting offset value
to 0 from initiator after sending REQ signal
3. Phase Controller
This controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out
phases executed on the SCSI bus.
4. Transfer Controller
This controller controls the information (data, command, status, message) transfer phases executed on the SCSI
bus.
There are two types of transfer for executing the information transfer phases.
• Asynchronous transfer : Control by interlocking REQ and ACK signals
• Synchronous transfer : Control with maximum of 32-byte offset value in data-in/out phase
Depending on the data migration, there are the following two modes.
• Program transfer : Performed via MPU interface using data registers
• DMA transfer : Performed via DMA interface using DREQ and DACK pins
At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal
sent from SPC in synchronous transfer, and maximum value between REQ and ACK signals in synchronous
transfer) can be saved for each ID and are automatically set when the data phase is started. The transfer byte
count is determined by block length × number of blocks.
5. Various Registers
• Command register
This register specifies each command with an 8-bit code.
When using the user program, specify “1” at the Bit 7. The lower 7 bits (Bit 6 to Bit 0) are invalid.
• Nexus status register
This register indicates the chip’s operating condition, the nexused partner’s ID, and data register status.
• SCSI control signal status register
This register indicates the status of SCSI control signals.
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