MB39A106 Datasheet, PDF (14/46 Pages) Fujitsu Component Limited. – 2-Channel DC/DC Converter IC with Overcurrent Protection Symmetrical-Phase Type

MB39A106
2. Channel Control Function
Channels, main, VB and PWRGOOD are turned on and off depending on the voltage levels at the CTL terminal
(pin 6), CTL1 terminal (pin 9) and CTL2 terminal (pin 10).
Channel On/Off Setting Conditions
CTL
CTL1
CTL2
Power
CH1
CH2
VB
PWRGOOD
L
⎯*
⎯*
OFF
OFF
OFF
OFF
OFF
H
L
L
ON
H
H
L
ON
H
L
H
ON
H
H
H
ON
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
*: Undefined
3. Protective Functions
(1) Undervoltage lockout protection circuit (UVLO)
The transient state or a momentary drops in supply voltage, which occurs when the power supply is turned on,
may cause the control IC to malfunction, resulting in breakdown or degradation of the system. To prevent such
malfunctions, the undervoltage lockout protection circuit detects the internal reference voltage level with respect
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the
CSCP terminal (pin 11) at the “L” level and setting the PWRGOOD terminal (pin 12) to the “L” level.
The system is restored when the supply voltage reaches the threshold voltage of the undervoltage lockout
protection circuit.
(2) Timer-latch overcurrent protection circuit block (OCP)
The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an
overcurrent flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source
using the main-side FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP connected
to the CSCP terminal (pin 11). If the overcurrent remains flowing beyond the predetermined period of time, the
circuit sets the latch to turn off the FETs on the main side and synchronous rectification side of each channel
while setting the PWRGOOD terminal (pin 12) to the “L” level. The detection current value can be set by resistor
RLIM1 connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and resistor RLIM2 connected
between the drain and the ILIM2 terminal (pin 23).
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “1. Setting Timer-
Latch Overcurrent Detection Current” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
(3) Timer-latch short-circuit protection circuit (SCP)
The short-circuit detection comparator (SCP Comp.) detects the output voltage level and, if the error amplifier
output voltage of either channel reaches the short-circuit detection voltage (typically 3.1 V), the timer circuit is
actuated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 11).
When the capacitor voltage reaches about 0.7 V, the circuit turns off the output transistor and sets the dead time
to 100%.
The PWRGOOD terminal (pin 12) is fixed at the “L” level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
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