MB86613 Datasheet, PDF (11/36 Pages) Fujitsu Component Limited. – IEEE 1394 Open HCI Controller

MB86613
1. PCI Interface Pin Description
Pin name
I/O
Function
AD31 to AD0
I/O 32-bit data/address multiplexed signal
C/BE3# to C/BE0# I/O Bus-command and byte-enable multiplexed signal
PCICLK
I
PCI bus clock input pin (Up to 33 MHz)
RST#
I
System reset input pin
PAR
I/O
Even parity bit for AD31:0 and C/BE3:0.
Enabled one PCI clock signal after address phase.
FRAME#
I/O Signal indicating that the bus is being driven by the master.
IRDY#
I/O Master data ready signal
TRDY#
I/O Target data ready signal
STOP#
I/O Target-to-master data transfer stop request signal
IDSEL
I
Chip select signal for accessing the configuration register
DEVSEL#
During target operation: Output signal indicating that the this device has been
I/O
selected.
During master operation: Input signal indicating that the device connected to the
PCI bus has been selected.
REQ#
O
Output signal requesting the bus arbiter for using the PCI bus
GNT#
I
Input signal for bus arbiter’s response to REQ#
PERR#
I/O Data parity error I/O signal
SERR#
OD Address parity error I/O signal
INTA#
OD Interrupt output signal
PME#
OD Power supply request signal in power save mode
2. Memory Interface Pin Description
Pin name
I/O
Function
MA15 to MA0
O
Externally-connected EPROM (BIOS ROM) address signal
MD7 to MD0
I/O
Externally-connected EPROM (BIOS ROM) data signal
MEMWE#
O
Connect this pin to the WE pin on the externally-connected EPROM (BIOS ROM)
MEMOE#
O
Connect this pin to the OE pin on the externally-connected EPROM (BIOS ROM)
MEMCS#
O
Connect this pin to the CS pin on the externally-connected EPROM (BIOS ROM)
EECS
O
Connect this pin to the CS pin on the externally-connected EEPROM
(PCI configuration ROM)
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