MB82D01171A Datasheet, PDF (10/27 Pages) Fujitsu Component Limited. – 16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory

MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
(2) Write Operation
Parameter
Symbol
-80/-80L/
-80LL
-85/-85L/
-85LL
-90/-90L/
-90LL
Unit
Min Max Min Max Min Max
Notes
Write Cycle Time
Address Setup Time
Address Hold Time
CE1 Write Setup Time
CE1 Write Hold Time
WE Setup Time
WE Hold Time
LB and UB Setup Time
LB and UB Hold Time
OE Setup Time
OE Hold Time
OE High to CE1 Low Setup Time
Address Hold Time to OE High
CE1 Write Pulse Width
WE Write Pulse Width
CE1 Write Recovery Time
WE Write Recovery Time
Data Setup Time
Data Hold Time
CE1 High Pulse Width
tWC
tAS
tAH
tCS
tCH
tWS
tWH
tBS
tBH
tOES
tOEH
tOEH[ABS]
tOHCL
tOHAH
tCW
tWP
tWRC
tWR
tDS
tDH
tCP
90  90  90  ns
*1
0  0  0  ns
*2
45  45  45  ns
*2
0 1000 0 1000 0 1000 ns
0 1000 0 1000 0 1000 ns
0  0  0  ns
0  0  0  ns
−5  −5  −5  ns
−5  −5  −5  ns
0 1000 0 1000 0 1000 ns
*3
45 1000 45 1000 45 1000 ns *3, *4
20  20  20  ns
*5
−3  −3  −3  ns
*6
0  0  0  ns
*7
60  60  60  ns *1, *8
60  60  60  ns *1, *8
15  15  15  ns *1, *9
15 1000 15 1000 15 1000 ns *1, *3, *9
20  20  20  ns
0  0  0  ns
20  20  20  ns
*9
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
*2: New write address is valid from either CE1 or WE is brought to High.
*3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High.
*4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual
value from specified minimum value.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low.
*6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
*7: Applicable if CE1 stays Low after read operation.
*8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively.
*9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively.
The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High.
In such case, the tCP (Min) must be satisfied.
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