MB15E07SR Datasheet, PDF (10/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler

MB15E07SR
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) A7 A6 A5 A4 A3 A2 A1
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Table 5. Prescaler Data Setting
SW
Prescaler divide ratio
1
32/33
0
64/65
Table 6. Charge Pump Current Setting
CS
Current value
1
±4.0 mA
0
±1.0 mA
Table 7. LD/fout Output Select Data Setting
LDS
LD/fOUT output signal
1
fout signal
0
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level
(DO) is reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The
relationship between the FC bit and DO is shown below.
Table 8. FC Bit Data Setting (LDS = “1”)
FC = 1
FC = 0
DO
LD/fout
DO
LD/fout
fr > fP
H
L
fr < fP
L
fout = fr
H
fout = fp
fr = fP
Z*
Z*
*: High impedance
10