UMFT240XE Datasheet, PDF (5/18 Pages) Future Technology Devices International Ltd. – UMFT240XE USB to 8-bit 245 FIFO Development Module

UMFT240XE
Version 1.0
Document Reference No.: FT_000653 Clearance No.: FTDI# 295
4.2 Signal Descriptions
Pin No.
Name
Type
Description
J1-1, J1-7,
J2-5
GND
PWR
Module Ground Supply Pins
J1-2
3V3OUT
Power
Input/
Output
3.3V output from integrated LDO regulator. This pin is decoupled with a 100nF
capacitor to ground on the PCB module. The prime purpose of this pin is to
provide the 3.3V supply that can be used internally. For power supply
configuration details see section 5.
J1-3
VCCIO
Power
Input
+1.8V to +3.3V supply to the UART Interface and CBUS I/O pins. For power
supply configuration details see section 5.
J1-4
DATA7
I/O
245 FIFO Bi-Directional data bit 7.
J1-5
DATA6
I/O
245 FIFO Bi-Directional data bit 6.
J1-6
DATA5
I/O
245 FIFO Bi-Directional data bit 5.
J1-8
DATA4
I/O
245 FIFO Bi-Directional data bit 4.
J1-9
DATA3
I/O
245 FIFO Bi-Directional data bit 3.
J1-10
DATA2
I/O
245 FIFO Bi-Directional data bit 2.
J1-11
DATA1
I/O
245 FIFO Bi-Directional data bit 1.
J1-12
DATA0
I/O
245 FIFO Bi-Directional data bit 0.
J2-1
SLD
GND
USB Cable Shield. Connected to GND via a 0ohm resistor.
J2-2
VBUS
Power
Output
5V Power output from the USB bus. For a low power USB bus powered design, up
to 100mA can be sourced from the 5V supply and applied to the USB bus. A
maximum of 500mA can be sourced from the USB bus in a high power USB bus
powered design. Currents up to 1A can be sourced from a dedicated charger and
applied to the USB bus.
J2-3
VCC
Power
Input
5V power input for FT240X. For power supply configuration details see section 5.
J2-4
RESET# Input
FT231X active low reset line. Configured with an on board pull-up and
recommended filter capacitor. When no power is applied to the USB bus reset, will
be held low, this prevents current from flowing to the host or hub when in self-
powered mode.
J2-5
CBUS6
I/O
Configurable CBUS I/O Pin. Function of this pin is configured in the device internal
MTP ROM. Factory Default pin Function is Keep_Awake. See CBUS Signal Options,
Table 4.2.
J2-6
CBUS5
I/O
Configurable CBUS I/O Pin. Function of this pin is configured in the device internal
MTP ROM. Factory Default pin Function is VBUS_Sense. See CBUS Signal Options,
Table 4.2.
J2-8
SI/WU
Output Send Immediate/Wake Up
J2-9
WR#
Input
245 FIFO Write status line
J2-10
RD#
Input
245 FIFO Read status line
J2-11
TXE#
Output 245 FIFO Transmit control line
J2-12
RXF#
Output 245 FIFO Receive control line
Table 4.1 – Module Pin Out Description
5
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