MC9S08AC16_09 Datasheet, PDF (99/330 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
7
6
5
4
3
2
1
R
R
R
R
R
PTDDS3
PTDDS2
PTDDS1
W
Reset
0
0
0
0
0
0
0
Figure 6-29. Output Drive Strength Selection for Port D (PTDDS)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
0
PTDDS0
0
Table 6-20. PTDDS Register Field Descriptions
Field
Description
3:0
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
PTDDS[3:0] output drive for the associated PTD pin.
0 Low output drive enabled for port D bit n.
1 High output drive enabled for port D bit n.
6.7.9 Port E I/O Registers (PTED and PTEDD)
Port E parallel I/O function is controlled by the registers listed below.
R
W
Reset
7
PTED7
0
6
PTED6
5
PTED5
4
PTED4
3
PTED3
2
PTED2
0
0
0
0
0
Figure 6-30. Port E Data Register (PTED)
1
PTED1
0
0
PTED0
0
Table 6-21. PTED Register Field Descriptions
Field
Description
7:0
PTED[7:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
99