MC9S08AC16_09 Datasheet, PDF (77/330 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
Table 5-11. Real-Time Interrupt Frequency
RTIS2:RTIS1:RTIS0
1-kHz Clock Source Delay¹
Using External Clock Source Delay
(Crystal Frequency)
0:0:0
Disable periodic wakeup timer
Disable periodic wakeup timer
0:0:1
8 ms
divide by 256
0:1:0
32 ms
divide by 1024
0:1:1
64 ms
divide by 2048
1:0:0
128 ms
divide by 4096
1:0:1
256 ms
divide by 8192
1:1:0
512 ms
divide by 16384
1:1:1
1.024 s
divide by 32768
1 _{Normal values are shown in this column based on fRTI = 1 kHz. See Appendix A, “Electrical Characteristics and}
Timing Specifications,” f_RTI for the tolerance on these values.
5.9.8 System Power Management Status and Control 1 Register (SPMSC1)
1
7
6
5
4
3
2
1
R LVDF
W
0
LVDACK
LVDIE
LVDRE²
LVDSE²
LVDE²
Reset
0
0
0
1
1
1
0
= Unimplemented or Reserved
1 _{Bit 1 is a reserved bit that must always be written to 0.}
2 _{This bit can be written only one time after reset. Additional writes are ignored.}
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
0
BGBE
0
Table 5-12. SPMSC1 Register Field Descriptions
Field
Description
7
LVDF
6
LVDACK
5
LVDIE
4
LVDRE
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
77