MC9S08GT16ACBE Datasheet, PDF (98/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
PTGSE3 PTGSE2 PTGSE1
0
0
0
0
0
0
Figure 6-30. Slew Rate Control Enable for Port G (PTGSE)
0
PTGSE0
0
Table 6-23. PTGSE Field Descriptions
Field
Description
3:0
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
PTGSE[3:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
7
6
5
4
3
2
1
R
0
0
0
0
PTGDD3 PTGDD2 PTGDD1
W
Reset
0
0
0
0
0
0
0
Figure 6-31. Data Direction for Port G (PTGDD)
1 _{Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD.}
0
PTGDD0
Note ⁽¹⁾
0
Table 6-24. PTGDD Field Descriptions
Field
Description
3:0
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[3:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
98
Freescale Semiconductor