MC9S08GT16ACBE Datasheet, PDF (94/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
PTDSE4
PTDSE3
PTDSE2
PTDSE1
0
0
0
0
0
0
Figure 6-22. Slew Rate Control Enable for Port D (PTDSE)
0
PTDSE0
0
Table 6-15. PTDSE Field Descriptions
Field
Description
4:0
PTDSE[4:0]
Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0
0
0
0
0
0
0
Figure 6-23. Data Direction for Port D (PTDDD)
Table 6-16. PTDDD Field Descriptions
Field
Description
4:0
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[4:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
94
Freescale Semiconductor