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MC9S08GT16ACBE Datasheet, PDF (136/300 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Internal Clock Generator (S08ICGV4)
R
W
Reset
Field
7:0
FLT
7
6
5
4
3
2
1
0
FLT
1
1
0
0
0
0
0
0
Figure 9-11. ICG Lower Filter Register (ICGFLTL)
Table 9-6. ICGFLTL Register Field Descriptions
Description
Filter Value â The FLT bits indicate the current ï¬lter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit ï¬lter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete. The ï¬lter registers show the ï¬lter value (FLT).
9.3.6 ICG Trim Register (ICGTRM)
7
6
5
4
3
2
1
0
R
TRIM
W
POR
1
0
0
0
0
0
0
0
Reset:
U
U
U
U
U
U
U
U
U = Unaffected by MCU reset
Figure 9-12. ICG Trim Register (ICGTRM)
Table 9-7. ICGTRM Register Field Descriptions
Field
7
TRIM
Description
ICG Trim Setting â The TRIM bits control the internal reference generator frequency. They allow a ±25%
adjustment of the nominal (POR) period. The bitâs effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.
9.4 Functional Description
This section provides a functional description of each of the ï¬ve operating modes of the ICG. Also
discussed are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG
is very ï¬exible, and in some conï¬gurations, it is possible to exceed certain clock speciï¬cations. When
using the FLL, conï¬gure the ICG so that the frequency of ICGDCLK does not exceed its maximum value
to ensure proper MCU operation.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
136
Freescale Semiconductor
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