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MC9S08GT16ACBE Datasheet, PDF (70/300 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Resets, Interrupts, and System Conï¬guration
When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and
conï¬gured for low bandwidth operation (RANGE = 0).
The SRTISC register includes a read-only status ï¬ag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable,
RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to
RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated.
See Section 5.7.6, âSystem Real-Time Interrupt Status and Control Register (SRTISC),â for detailed
information about this register.
5.7 Register Deï¬nition
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, âMemoryâ of this data sheet for the absolute
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header ï¬le is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, âModes of Operation.â
MC9S08GT16A/GT8A Data Sheet, Rev. 1
70
Freescale Semiconductor
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