56F8366_09 Datasheet, PDF (97/182 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—
Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.6.8 SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.7 Interrupt Priority Register 6 (IPR6)
Base + $6
Read
Write
RESET
15 14 13 12 11 10 9
8
7
6
5
0
TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRD0 IPL
4
3
2
1
0
0 _{DEC0_XIRQ DEC0_HIRQ}
IPL
IPL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
56F8366 Technical Data, Rev. 7
Freescale Semiconductor
97
Preliminary