|
56F8366_09 Datasheet, PDF (102/182 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers | |||
|
◁ |
5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)â
Bits 13â12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 0
⢠10 = IRQ is priority level 1
⢠11 = IRQ is priority level 2
5.6.9.3 ReservedâBits 11â10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)â
Bits 9â8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 0
⢠10 = IRQ is priority level 1
⢠11 = IRQ is priority level 2
5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)â
Bits 7â6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 0
⢠10 = IRQ is priority level 1
⢠11 = IRQ is priority level 2
5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)âBits 5â4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 0
⢠10 = IRQ is priority level 1
⢠11 = IRQ is priority level 2
56F8366 Technical Data, Rev. 7
102
Freescale Semiconductor
Preliminary
|
▷ |