56F8366_09 Datasheet, PDF (125/182 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
GPIOC_PER Register
GPIO Controlled
SIM_ GPS Register
Quad Timer Controlled
0
0
I/O Pad Control
1
SPI Controlled
1
Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control
Table 6-2 Control of GPIOC Pads Using SIM_GPS Control ¹
Control Registers
Pin Function
Comments
GPIO Input
0
0
—
—
GPIO Output
0
1
—
—
Quad Timer Input / 1
—
Quad Decoder
Input ²
Quad Timer Output 1
—
/ Quad Decoder
Input ³
0
0
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
0
1
SPI input
SPI output
1
—
1
—
1
— See SPI controls for determining the direction
of each of the SPI pins.
1
—
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control
bits is used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
56F8366 Technical Data, Rev. 7
Freescale Semiconductor
125
Preliminary