MC9S12KT256 Datasheet, PDF (91/594 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 2-16. FSTAT Field Descriptions
Field
Description
7
CBEIF
Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command
buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing
a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned
word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause
the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR
flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request
(see Figure 2-30).
0 Buffers are full.
1 Buffers are ready to accept a new command.
6
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The
CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending
commands. The CCIF flag does not set when an active commands completes and a pending command is
fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together
with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-30).
0 Command in progress.
1 All commands are completed.
5
PVIOL
Protection Violation Flag — The PVIOL flag indicates an attempt was made to program or erase an address
in a protected area of the Flash block during a command write sequence. The PVIOL flag is cleared by writing a
1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch
a command or start a command write sequence.
0 No failure.
1 A protection violation has occurred.
4
ACCERR
Access Error Flag — The ACCERR flag indicates an illegal access to the Flash array caused by either a
violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in
the FCMD register), launching the sector erase abort command terminating a sector erase operation early,
detection of a double fault or the execution of a CPU STOP instruction while a command is executing (CCIF =
0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on
ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If
ACCERR is set by the detection of a double fault, an erase verify operation or a data compress operation, any
buffered command will not launch.
0 No access error detected.
1 Access error has occurred.
3
DFDIF
Double Fault Detect Interrupt Flag — The DFDIF flag indicates that one of the following Flash block operations
has detected a double bit fault in the stored parity and data bits.
• Array Read.
• Erase Verify.
• Data Compress.
• Reset Sequence (reads of the protection and security fields stored in the Flash memory).
When the DFDIF flag is set during a Flash array read operation, the data read from the Flash module are the
data bits read out of the Flash array without correction and should be considered invalid. When the DFDIF flag
is set during a Flash array read, erase verify, data compress or reset sequence operation, the Flash block
address containing the parity and data bits that caused the DFDIF flag to set will be stored in the FADDR register
and the parity bits will be stored in the FDATA register. The DFDIF flag is cleared by writing a 1 to the ACCERR
bit which is set when the DFDIF flag is set. Writing a “0” to the DFDIF flag has no effect on DFDIF. The DFDIF
flag is used together with the DFDIE enable bit to generate an interrupt request (see Figure 2-30). While DFDIF
is set, Flash array read operations are allowed. If DFDIF is not cleared and another double bit fault is detected,
the FADDR and FDATA registers will maintain the contents from the fault that caused the DFDIF bit to set.
0 No double bit fault detected.
1 Double bit fault detected.
MC9S12KT256 Data Sheet, Rev 1.15
Freescale Semiconductor
91