MC9S12KT256 Datasheet, PDF (75/594 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2
256 Kbyte ECC Flash Module (S12FTS256K2ECCV2)
2.1 Introduction
This document describes the FTS256K2ECC module that includes a 256 Kbyte Flash (nonvolatile)
memory with built-in Error Code Correction (ECC). The Flash memory may be read as either bytes,
aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and
two bus cycles for misaligned words.
The Flash memory is ideal for program and data storage for single-supply applications allowing for field
reprogramming without requiring external voltage sources for program or erase. Program and erase
functions are controlled by a command driven interface. The Flash module supports both block erase and
sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program
and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is
being erased or programmed.
The ECC logic is included in the Flash module with the program and erase operations automatically
generating the ECC parity bits. The ECC logic implements a modified Hamming code capable of
correcting single bit faults and detecting double bit faults in each word of the Flash memory.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed and will
result in invalid data stored.
2.1.1 Glossary
Banked Register — A memory-mapped register operating on one Flash block which shares the same
register address as the equivalent registers for the other Flash blocks. The active register bank is selected
by the BKSEL bit in the FCNFG register.
Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms
(including program and erase) on the Flash memory.
Common Register — A memory-mapped register which operates on all Flash blocks.
2.1.2 Features
• 256 Kbytes of Flash memory comprised of two 128 Kbyte blocks with each block divided into 128
sectors of 1024 bytes with every word (two bytes) accompanied by 6 ECC parity bits
• Single bit fault correction per word during read operations
MC9S12KT256 Data Sheet, Rev 1.15
Freescale Semiconductor
75