MC9S12KT256 Datasheet, PDF (30/594 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 MC9S12KT256 Device Overview (MC9S12KT256V1)
1.2.2.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
1.2.2.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Freescale representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
MCU
R
CP
CS
VDDPLL
VDDPLL
Figure 1-5. PLL Loop Filter Connections
1.2.2.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
1.2.2.7 PAD[15:8] / AN1[7:0] — Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8
channels (ATD1).
1.2.2.8 PAD[7:0] / AN0[7:0] — Port AD Input Pins [7:0]
PAD7–PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8
channels (ATD0).
1.2.2.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7–PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
1.2.2.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7–PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
MC9S12KT256 Data Sheet, Rev. 1.15
30
Freescale Semiconductor