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MC9S12KT256 Datasheet, PDF (100/594 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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2.4.1.2 Command Write Sequence
The Flash command controller is used to supervise the command write sequence to execute program,
erase, erase verify, and data compress algorithms.
Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be
clear (see Section 2.3.2.7, âFlash Status Register (FSTAT)â) and the CBEIF flag must be tested to
determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the
buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the
buffers are not available, a new command write sequence will overwrite the contents of the address, data,
and command buffers.
A command write sequence consists of three steps which must be strictly adhered to with writes to the
Flash module not permitted between the steps. However, Flash register and array reads are allowed during
a command write sequence. A command write sequence consists of the following steps:
1. Write an aligned data word to a valid Flash array address. The address and data will be stored in
the address and data buffers, respectively. If the CBEIF ï¬ag is clear when the Flash array write
occurs, the contents of the address and data buffers will be overwritten and the CBEIF ï¬ag will be
set.
2. Write a valid command to the FCMD register.
a) For the erase verify command (see Section 2.4.1.3.1, âErase Verify Commandâ), the contents
of the data buffer are ignored and all address bits in the address buffer are ignored.
b) For the data compress command (see Section 2.4.1.3.2, âData Compress Commandâ), the
contents of the data buffer represents the number of consecutive words to read for data
compression and the contents of the address buffer represents the starting address.
c) For the program command (see Section 2.4.1.3.3, âProgram Commandâ), the contents of the
data buffer will be programmed to the address speciï¬ed in the address buffer with all address
bits valid.
d) For the sector erase command (see Section 2.4.1.3.4, âSector Erase Commandâ), the contents
of the data buffer are ignored and address bits [9:0] contained in the address buffer are ignored.
e) For the mass erase command (see Section 2.4.1.3.5, âMass Erase Commandâ), the contents of
the data buffer and address buffer are ignored.
f) For the sector erase abort command (see Section 2.4.1.3.6, âSector Erase Abort Commandâ),
the contents of the data buffer and address buffer are ignored.
3. Clear the CBEIF ï¬ag by writing a 1 to CBEIF to launch the command. When the CBEIF ï¬ag is
cleared, the CCIF ï¬ag is cleared on the same bus cycle by internal hardware indicating that the
command was successfully launched. For all command write sequences except data compress and
sector erase abort, the CBEIF ï¬ag will set four bus cycles after the CCIF ï¬ag is cleared indicating
that the address, data, and command buffers are ready for a new command write sequence to begin.
For data compress and sector erase abort operations, the CBEIF ï¬ag will remain clear until the
operation completes.
A command write sequence can be aborted prior to clearing the CBEIF ï¬ag by writing a 0 to the CBEIF
ï¬ag and will result in the ACCERR ï¬ag being set.
MC9S12KT256 Data Sheet, Rev 1.15
100
Freescale Semiconductor
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