33661 Datasheet, PDF (9/21 Pages) Freescale Semiconductor, Inc – Local Area Network (LIN) Enhanced Physical Interface with Selectable Slew Rate

TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
Recessive State
V_REC
LIN
t _DOM(MIN)
RXD
58.1% V_SUP
40% V_SUP
t _DOM(MAX)
28.4% V_SUP
V_DOM
Dominant State
t _REC(MIN)
t _REC(MAX)
74.4% V_SUP
60% V_SUP
42.2% V_SUP
t_RL
t_RH
Figure 4. Normal Mode Bus Timing Characteristics
TXD
Recessive State
V_REC
LIN
t _DOM(MIN)
RXD
61.6% V_SUP
40% V_SUP
t _DOM(MAX)
25.1% V_SUP
V_DOM
Dominant State
t _REC(MIN)
t _REC(MAX)
77.8% V_SUP
60% V_SUP
38.9% V_SUP
t _RL
t _RH
Figure 5. Slow Mode Bus Timing Characteristics
V_SUP
VSUP
TXD
R₀
RXD
LIN
GND
C₀
Note R₀ and C₀: 1.0 kΩ/1.0 nF, 660 Ω/6.8 nF, and 500 Ω/10 nF.
Figure 6. Test Circuit for Timing Measurements
Analog Integrated Circuit Device Data
Freescale Semiconductor
33661
9