PXR40PB Datasheet, PDF (8/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Real-Time Applications

Features
Alternatively, input events can be used to capture the time base, allowing measurement of an input signal.
The eMIOS provides the following features:
• 32 unified channels, featuring:
— 24-bit registers for capture/match values
— 24-bit internal counter
— Global prescaler
— Pin for input/output (each channel signal is routed to a pin, however, most pins are also
multiplexed with other signals)
— Selectable time base
— Can generate its own time base
• Five 24-bit wide counter buses
— Counter bus A can be driven by unified channel 23
— Counter bus B, C, D and E are driven by unified channels 0, 8, 16, and 24, respectively
— Counter bus A can be shared among all unified channels. UCs 0 to 7, 8 to 15, 16 to 23, and 24
to 31 can share counter buses B, C, D and E, respectively
• Shared time bases with the eTPU
• Synchronization among internal and external time bases
• Shadow FLAG register
• State of block can be frozen for debug purposes
2.5.6 Enhanced timing processor unit (eTPU2)
Two eTPU2 modules are available on the PXR40. The eTPU2 is the second generation of the enhanced
timing co-processors (eTPU) that were used on the MPC5500 family. eTPU2 is fully upward compatible
with eTPU, runs the same binary code image, and can be used with the same tool suite. eTPU2 includes
many enhancements to improve efficiency of compilers, functionality, ease of programming and
operability while maintaining the same overall architecture. Some of these enhancements may be accessed
using the existing compiler tool chain, while other enhancements require updates to the compiler.
The eTPU2 includes these distinctive features:
• 32 standard channels, each channel is associated with one input and one output signal
• Two independent 24-bit time bases for channel synchronization:
• Event-triggered microengine
— 24 KB of code memory (SCM)
— 6 KB of shared parameter (data) RAM (SPRAM)
• Resource sharing features support channel use of common channel registers, memory and
microengine time
— Hardware scheduler works as a task management unit, dispatching event service routines by
pre-defined, host-configured priority
PXR40 Product Brief, Rev. 1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor