PXR40PB Datasheet, PDF (14/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Real-Time Applications

Features
— Zero to eight bytes data length
— Programmable bit rate as fast as 1 Mb/sec
— Content-related addressing
• Each MB configurable as receive (Rx) or transmit (Tx), all supporting standard and extended
messages
• Individual Rx mask registers per message buffer
• Includes 1056 bytes of RAM used for message buffer storage
• Includes 256 bytes of RAM used for individual Rx mask registers
• Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either eight extended,
16 standard, or 32 partial (8 bits) IDs, with individual masking capability
• Selectable backwards compatibility with previous CAN version
• Programmable clock source to the CAN protocol interface, either bus clock or crystal oscillator
• Unused message buffer and Rx mask register space can be used as general-purpose RAM space
• Listen-only mode capability
• Programmable loop-back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or local priority on
individual Tx message buffers.
• Hardware cancellation on Tx message buffers.
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low-power modes, with programmable wake-up on bus activity
2.5.14 Enhanced direct memory access controller (eDMA2)
The following summarizes the PXR40’s implementation of the eDMA2 controller:
• Second-generation modules capable of performing complex data movements via 64 programmable
channels (eDMA2-A) and 32 programmable channels (eDMA2-B), without intervention from the
host processor
• DMA engine
— Performs source and destination address calculations
— Performs data movement operations
• Includes SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses, transfer size, plus support for enhanced
addressing modes
PXR40 Product Brief, Rev. 1
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor