PXR40PB Datasheet, PDF (21/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Real-Time Applications

Features
• A TAP controller state machine that controls the operation of the data registers, instruction register
and associated circuitry.
• Censorship inhibit register
— 64-bit censorship password register
— If the external tool writes a 64-bit password that matches the serial boot password stored in the
internal flash memory shadow row, censorship is disabled until the next JTAG reset
2.5.23 Nexus
The Nexus debug interface (NDI) block provides real-time development support capabilities for the
PXR40 in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NDI block is an
integration of several individual Nexus blocks that are selected to provide the development support
interface for the PXR40. The NDI block interfaces to the host processor, the eTPU, and internal buses to
provide development support as per the IEEE-ISTO 5001-2003 standard. The development support
provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCU’s internal memory map and access to the Power Architecture and eTPU internal registers during halt.
The Nexus interface also supports a JTAG-only mode using only the JTAG pins. Nexus also provides data
trace support for flexray and both eDMA2s. The following features are implemented:
• 23 or 27 full duplex pin interface for medium and high visibility throughput
— One of two modes selected by register configuration:
– Reduced-port mode (RPM) comprises 12 MDO (message data out) pins
– Full-port mode (FPM) comprises 16 MDO pins
— Auxiliary output port
• Debug support pins
— One MCKO (message clock out) pin
— 12 or 16 MDO (message data out) pins
— Two MSEO (message start/end out) pins
— One RDY (ready) pin
— One EVTO (event out) pin
– Auxiliary input port
— One EVTI (event in) pin
— 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) or 3-pin (JCOMP, TMS, and TCK)
— Reduced-pin JTAG mode as per IEEE 1149.7
• Host processor (e200z7) standard class 3 compliant
• eTPU development support standard class 3 compliant
• Supports data trace for the FlexRay controller and both eDMA2 modules
• Run-time access to the on-chip memory map via the Nexus read/write access protocol
• All features are independently configurable and controllable via the IEEE 1149.1 I/O port
• The NDI block reset is controlled with JCOMP, power-on reset, and the TAP state machine. All
these sources are independent of system reset.
PXR40 Product Brief, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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