PXR40PB Datasheet, PDF (1/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Real-Time Applications

Freescale Semiconductor
Product Brief
Document Number: PXR40PB
Rev. 1, 06/2011
PXR40 Product Brief
32-bit Power Architecture^® Microcontrollers for Real-Time
Applications
The PXR40 series 32-bit microcontrollers provide
Contents
integrated analog and processing power to give industrial 1 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
users a reliable, robust controller solution to meet a
variety of timing critical application needs, such as
motion/motor control, without sacrificing performance
during complex operations. Based on Power
Architecture^®, these system-on-chip devices are 100%
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 PXR40 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 PXR40 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Critical Performance Parameters. . . . . . . . . . . . . . . 6
2.4 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Developer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
user-mode compatible with the classic Power
Architecture instruction set.
4 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
The e200z7 host processor core of the PXR40 is
compatible with the Power Architecture^® Book E
architecture. It is 100% user-mode compatible (with
floating point library) with the classic PowerPC
instruction set. The Book E architecture has
enhancements that improve the architecture’s fit in
embedded applications. In addition to the classic
PowerPC instruction set, this core also has additional
instruction support for digital signal processing (DSP).
The PXR40 has two levels of memory hierarchy, a
16 KB instruction + 16 KB data cache in a Harvard
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Preliminary—Subject to Change Without Notice