MC33927 Datasheet, PDF (8/44 Pages) Freescale Semiconductor, Inc – Three-Phase Field Effect Transistor Pre-Driver

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 8.0V ≤ V_PWR = V_BAT ≤ 40V, -40°C ≤ T_A ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
VBAT Supply Voltage Startup Threshold⁽⁸⁾
VBAT Supply Current, V_PWR = V_BAT = 40V
RST and ENABLE = 5.0V
No output loads on Gate Drive Pins, No PWM
No output loads on Gate Drive Pins, 20kHz, 50% Duty Cycle
VPWR Supply Current, V_PWR = V_BAT = 40V
RST and ENABLE = 5.0V
No output loads on Gate Drive Pins, No PWM
Output Loads = 620nC per FET, 20kHz PWM⁽⁹⁾
Sleep State Supply Current, RST = 0V
V_BAT = 40V
V_PWR = 40V
Sleep State Output Gate Voltage
IG < 100µA
V_{BAT_ST}
–
I_BAT
–
–
I_{PWR_ON}
–
–
I_BAT
–
I_PWR
–
V_GATESS
–
6.0
8.0
V
mA
1.0
–
–
10
mA
11
20
–
95
µA
14
30
56
100
–
1.3
V
Trickle Charge Pump (Bootstrap Voltage)
V_BAT = 14V
Bootstrap Diode Forward Voltage at 10mA
VDD V INTERNAL REGULATOR
V_DD Output Voltage, V_PWR = 8V to 40V, C = 0.47µF⁽¹⁰⁾
External Load I_{DD_EXT} = 0 to 1.0mA
Internal V_DD Supply Current, V_DD = 5.5V, No External Load
VLS REGULATOR
V_Boot
V_F
V_DD
I_DD
22
28
32
V
–
–
1.2
V
4.5
–
5.5
V
–
–
12
mA
Peak Output Current, V_PWR = 16V, V_LS = 10V
Linear Regulator Output Voltage, I_VLS = 0 to 60mA⁽¹¹⁾
VLS Disable Threshold⁽¹²⁾
I_PEAK
350
600
800
mA
V_LS
13.5
15
17
V
V_THVLS
7.5
8.0
8.5
V
Notes
8. When minimum system voltage could be less than 14V operation with the Charge Pump is recommended. V_BAT must exceed this
threshold in order for the Charge Pump and V_DD regulator to startup and drive V_PWR to > 8.0V. Once V_PWR exceeds 8.0V, the circuits
will continue to operate even if V_BAT drops below 6.0V.
9. This parameter is guaranteed by design. It is not production tested.
10. Minimum external capacitor for stable V_DD operation is 0.47µF.
11. Recommended external capacitor for the V_LS regulator is 2.2µF low ESR at each pin VLS and VLS_CAP.
12. When V_LS is less than this value, the outputs are disabled and HOLDOFF circuits are active.
33927
8
Analog Integrated Circuit Device Data
Freescale Semiconductor