MC33927 Datasheet, PDF (13/44 Pages) Freescale Semiconductor, Inc – Three-Phase Field Effect Transistor Pre-Driver

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0V ≤ V_PWR = V_BAT ≤ 40V, -40°C ≤ T_A ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERNAL REGULATORS
V_DD Power-Up Time (Until INT High)
8.0V ≤ V_PWR ⁽³²⁾
VLS Power-Up Time
16V ≤ V_PWR ⁽³³⁾
t_{PU_VDD}
–
t_{PU_VDD}
–
ms
–
2.0
ms
–
2.0
CHARGE PUMP
Charge Pump Oscillator Frequency
Charge Pump Slew Rate⁽³⁴⁾
GATE DRIVE
F_OSC
90
125
190
kHz
SR_CP
–
100
–
V/µs
High-Side Turn-On Time
Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, (Figure 7)
t_ONH
–
ns
20
35
High-Side Turn-On Delay⁽³⁵⁾
Delay from Command to 1.0V, (Figure 7)
t_{D_ONH}
ns
130
265
386
High-Side Turn-Off Time
Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, (Figure 8)
t_OFFH
–
ns
20
35
High-Side Turn-Off Delay⁽³⁵⁾
Delay from Command to 10V, (Figure 8)
t_{D_OFFH}
ns
130
265
386
Low-Side Turn-On Time
Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, (Figure 7)
t_ONL
–
ns
20
35
Low-Side Turn-On Delay⁽³⁵⁾
Delay from Command to 1.0V, (Figure 7)
t_{D_ONL}
ns
130
265
386
Low-Side Turn-Off Time
Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, (Figure 8)
t_OFFL
–
ns
20
35
Low-Side Turn-Off Delay⁽³⁵⁾
Delay from Command to 10V, (Figure 8)
t_{D_OFFL}
ns
130
265
386
Same Phase Command Delay Match⁽³⁶⁾
Thermal Filter Duration ⁽³⁷⁾
t_{D_DIFF}
-20
0
+20
ns
t_DUR
8.0
–
30
µs
Notes
32. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V_DD.
33. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VLS. This
delay includes the expected time for V_DD to rise.
34. The charge pump operating at 12V V_bat, 1µF pump capacitor, MUR120 diodes and 47µF filter capacitor.
35. These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes
one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and
output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision
block. Synchronization time accounts for up to one clock period of variation. See Figure 6.
36. This is the maximum separation or overlap of the High and Low side gate drives due to propagation delays when commanding one ON
and the other OFF simultaneously.
37. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33927
13