MC33927 Datasheet, PDF(27/44 Page) Freescale Semiconductor, Inc – Three-Phase Field Effect Transistor Pre-Driver

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MC33927 Datasheet, PDF (27/44 Pages) Freescale Semiconductor, Inc – Three-Phase Field Effect Transistor Pre-Driver

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FUNCTIONAL INTERNAL BLOCK DESCRIPTION

INTRODUCTION

Figure 14. Short to Battery Detection

Phase Comparator

Faults could also be detected as Phase Errors. A phase

error is generated if the output signal (at Px_HS_S) does not

properly reflect the drive conditions.

A phase error is detected by a Phase Comparator. The

Phase Comparator compares the voltage at the Px_HS_S

node with a reference of one half the voltage at the VBAT pin.

A high side phase error (which will also trigger the

Desaturation Detector) occurs when the high side FET is

commanded on, and Px_HS_S is still low at the end of the

deadtime and blanking time duration. Similarly, a LS phase

error occurs when the low side FET is commanded on, and

the Px_HS_S is still high at the end of the deadtime and

blanking time duration.

The Phase Error Flag is the triple OR of phase errors from

each phase. Each phase error is the OR of the high side and

low side phase errors. This flag can generate an interrupt if

the appropriate mask bit is set. The INT will be held in the

High state until the fault is removed, and the appropriate bit

in the Status Register 0 is cleared by the CLINT1 command.

This fault reporting mechanism is described in detail in the

Logic Commands and Registers section.

HOLD OFF CIRCUIT

The IC guarantees the output FETs are turned off in the

absence of VDD or VPWR by means of the Hold off circuit. A

small current source, generated from VBAT, typically 100 ÂµA,

is mirrored and pulls all the output gate drive pins low when

VDD is less than about 3.0V, RST is active (low), or when VLS

is lower than the VLS_Disable threshold.

CHARGE PUMP

The Charge Pump circuit provides the basic switching

elements required to implement a charge pump when

combined with external capacitors and diodes for enhanced

low voltage operation.

When the 33927 is connected per the typical application

using the charge pump (see Figure 17), the regulation path

for VLS includes the charge pump and a linear regulator. The

regulation set point for the linear regulator is nominally at

15.34V. As long as VLS output voltage (VLSOUT) is greater

than the VLS analog regulator threshold (VLSATH) minus

VTHREG, the charge pump is not active.

If VLSOUT < VLSATH â VTHREG the charge pump turns ON

until VLSOUT > VLSATH â VTHREG + VHYST

VHYST is approximately 200mV. VLSATH will not interfere

with this cycle even when there is overlap in the thresholds

due to the design of the regulator system.

The maximum current the charge pump can supply is

dependent on the pump capacitor value and quality, the

pump frequency (nominally 130kHz) and the Rdson of the

pump FETs. The effective charge voltage for the pump

capacitor would be VBAT â 2*VDIODE. The total charge

transfer would then be CPUMP * (VBAT â 2*VDIODE).

Multiplying by the switch frequency gives the theoretical

current the pump can transfer: FPUMP * CPUMP * (VBAT â

2*VDIODE).

NOTE: There is also another smaller, fully integrated

charge pump (Trickle Charge Pump - see Figure 2), which is

used to maintain the high-side driversâ gate VGS in 100

percent duty cycle modes.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33927

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