MC9S12XEG128MAA Datasheet, PDF (792/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 22 Timer Module (TIM16B8CV2) Block Description
22.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin
This pin serves as input capture or output compare for channel 1.
22.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin
This pin serves as input capture or output compare for channel 0.
NOTE
For the description of interrupts see Section 22.6, “Interrupts”.
22.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
22.3.1 Module Memory Map
The memory map for the TIM16B8CV2 module is given below in Figure 22-5. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B8CV2 module and the address offset for each register.
22.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
TIOS
R
IOS7
W
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0x0001
CFORC
0x0002
OC7M
0x0003
OC7D
0x0004
TCNTH
0x0005
TCNTL
R
0
W FOC7
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
R
OC7M7
W
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
R
OC7D7
W
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10
W
R
TCNT7
W
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
0
FOC1
OC7M1
OC7D1
TCNT9
TCNT1
0
FOC0
OC7M0
OC7D0
TCNT8
TCNT0
= Unimplemented or Reserved
Figure 22-5. TIM16B8CV2 Register Summary (Sheet 1 of 3)
MC9S12XE-Family Reference Manual Rev. 1.25
792
Freescale Semiconductor