MC9S12XEG128MAA Datasheet, PDF (370/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
10.3.1.12 XGATE Program Counter Register (XGPC)
The XGPC register (Figure 10-14) provides access to the RISC core’s program counter.
Module Base +0x0001E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGPC
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-14. XGATE Program Counter Register (XGPC)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-14. XGPC Field Descriptions
Field
Description
15–0
Program Counter — The RISC core’s program counter
XGPC[15:0]
10.3.1.13 XGATE Register 1 (XGR1)
The XGR1 register (Figure 10-15) provides access to the RISC core’s register 1.
Module Base +0x00022
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR1
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-15. XGATE Register 1 (XGR1)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-15. XGR1 Field Descriptions
Field
Description
15–0
XGATE Register 1 — The RISC core’s register 1
XGR1[15:0]
MC9S12XE-Family Reference Manual Rev. 1.25
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