MC9S12XEG128MAA Datasheet, PDF (1251/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Appendix A Electrical Characteristics
Table A-31. Example 1b: Normal Expanded Mode Timing at 50MHz bus (EWAIT enabled)
V_DD5 = 5.0V
V_DD5 = 3.3V
No.
Characteristic
Symbol
C
2 stretch
cycles
3 stretch
2 stretch
cycles
C
cycles
3 stretch
cycles
Unit
Min Max Min Max
Min Max Min Max
- External cycle time (selected
t_cyce
- 60
∞
80
∞ - 120 ∞ 160 ∞ ns
by EXSTR)
1 External cycle time
(EXSTR+1EWAIT)
2 Address ⁽¹⁾ valid to RE fall
3 Pulse width, RE ⁽²⁾
4 Address valid to WE fall
5 Pulse width, WE
6 Read data setup time
(if ITHRS = 0)
t_cycew - 80
t_ADRE D 4
PW_RE D 68
t_ADWE D 4
PW_WE D 58
t_DSR D 19
∞ 100 ∞ - 160 ∞ 200 ∞ ns
-
4
- D 13
-
13
- ns
-
88
- D 138 - 178 - ns
-
4
- D 15
-
15
- ns
-
78
- D 118 - 158 - ns
-
19
- D 38
-
38
- ns
Read data setup time
t_DSR D 23
-
23
-D
N/A
ns
(if ITHRS = 1)
7 Read data hold time
t_DHR D 0
-
0
- D0
-
0
- ns
8 Read enable access time
t_ACCR D 49
-
69
- D 65
- 105 - ns
9 Write data valid to WE fall
t_WDWE D 5
-
5
- D5
-
5
- ns
10 Write data setup time
t_DSW D 63
-
93
- D 123 - 163 - ns
11 Write data hold time
t_DHW D 6
-
6
- D4
-
4
- ns
12 Address to EWAIT fall
t_ADWF D 0
16
0
36 D 0
20
0
- ns
13 Address to EWAIT rise
t_ADWR D 30 39 50 58 D 50 61 90 101 ns
1. Includes the following signals: ADDRx, UDS, LDS, and CSx.
2. Affected by EWAIT.
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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